Nol.A SDK Library 26.11.2
For IoT System Software Development
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Public Types | Public Member Functions | Static Public Attributes | Protected Types | Protected Member Functions | Protected Attributes | List of all members
SX1301Chip Class Reference
Supported Chip Drivers » SX1301

저전력 multi-band LoRaTM 및 FSK 무선 통신을 지원하는 Semtech의 SX1301 radio concentrator 을 지원합니다. More...

#include <SX1301Chip.hpp>

Inheritance diagram for SX1301Chip:
PacketRadioChip

Public Types

enum  Radio_t { RADIO_TYPE_NONE = 0 , RADIO_TYPE_SX1255 = 1 , RADIO_TYPE_SX1257 = 2 }
enum  {
  NUM_RF_CHAIN = 2 , NUM_IF_CHAIN = 10 , NUM_TX_GAIN = 16 , IF_INDEX_LORA_STANDALONE = 8 ,
  IF_INDEX_FSK_STANDALONE = 9
}
enum  {
  BW_UNDEFINED = 0 , BW_500kHz = 1 , BW_250kHz = 2 , BW_125kHz = 3 ,
  BW_62_5kHz = 4 , BW_31_2kHz = 5 , BW_15_6kHz = 6 , BW_7_8kHz = 7
}
enum  {
  DR_UNDEFINED = 0 , DR_LORA_SF7 = (1 << 1) , DR_LORA_SF8 = (1 << 2) , DR_LORA_SF9 = (1 << 3) ,
  DR_LORA_SF10 = (1 << 4) , DR_LORA_SF11 = (1 << 5) , DR_LORA_SF12 = (1 << 6) , DR_LORA_MULTI = 0x7E ,
  DR_FSK_MIN = 500 , DR_FSK_MAX = 250000
}
enum  { ERROR_IF_FREQ_TOO_HIGH = -100 , ERROR_IF_FREQ_TOO_LOW = -101 , ERROR_IF_BANDWIDTH_NOT_SUPPORTED = -102 , ERROR_IF_DATARATE_NOT_SUPPORTED = -103 }
enum  { ERROR_TX_GAIN_DIG = -100 , ERROR_TX_GAIN_DAC = -101 , ERROR_TX_GAIN_MIX = -102 , ERROR_TX_GAIN_PA = -103 }
enum  { MCU_AGC_FW_BYTE = 8192 , MCU_ARB_FW_BYTE = 8192 }

Public Member Functions

 SX1301Chip (SPI &s, int8_t pinCsn, int8_t pinReset, uint8_t clockSource)
error_t setSyncword (uint8_t value)
 Syncword를 설정합니다.
error_t setDataRate (Radio::LoRaSF_t sf)
 기본으로 사용할 LoRa spreading factor (SF)를 설정합니다.
error_t setCodingRate (Radio::LoRaCR_t cr)
 기본으로 사용할 LoRa coding rate (CR)를 설정합니다.
error_t setBandwidth (Radio::LoRaBW_t bw)
 기본으로 사용할 LoRa bandwidth (BW)를 설정합니다.
error_t configureRf (uint8_t index, bool enable, bool txEnable, uint32_t freqHz, float rssiOffset=-166.0, Radio_t type=RADIO_TYPE_SX1257, uint32_t txNotchFreqHz=0)
 RF interface를 설정합니다.
error_t configureRxIf (uint8_t index, uint8_t rfChainIndex, bool enable, int32_t rFreqHz, uint8_t bandwidth=BW_UNDEFINED, uint32_t datarate=DR_UNDEFINED, uint8_t fskSyncwordSize=3, uint64_t fskSyncword=0xC194C1)
 Rx interface를 설정합니다.
uint32_t getChannel (uint8_t index)
 Rx interface 별 설정된 주파수를 가져옵니다.
error_t configureTxGain (uint8_t index, uint8_t digGain, uint8_t paGain, uint8_t dacGain, uint8_t mixGain, int8_t dBm)
 Tx Gain look up table을 설정합니다.
error_t begin ()
 SX1301 의 동작을 시작합니다.
void end ()
 SX1301 의 동작을 종료합니다.
error_t readFrame (RadioPacket *pkt)
 수신 버퍼에서 프레임을 읽습니다.
bool bufferIsEmpty ()
void flushBuffer ()
void sleep ()
void wakeup ()
error_t transmit (RadioPacket *pkt)
error_t transmit (RadioPacket *frame, uint64_t txTimestamp)
bool cca () override
 채널이 혼잡한지 아닌지 검사합니다.
void setTxPower (int8_t dBm)
 송신 출력을 설정합니다.
int8_t getTxPower ()
 현재 설정된 송신 출력을 반환합니다.
void setChannel (uint32_t channel)
 채널을 설정합니다.
uint32_t getChannel ()
 현재 설정된 채널을 반환합니다.
Public Member Functions inherited from PacketRadioChip
void setCcaThreshold (int16_t dBthreshold)
virtual int64_t getDeviceTimestamp ()
 장치 내부의 timestamp 값을 읽습니다.

Static Public Attributes

static const uint8_t firmwareAgc [MCU_AGC_FW_BYTE]
static const uint8_t firmwareArb [MCU_ARB_FW_BYTE]
static const uint8_t firmwareCal [MCU_AGC_FW_BYTE]

Protected Types

enum  TxStatus_t { STATE_TX_OFF = 0 , STATE_TX_FREE = 1 , STATE_TX_EMITTING = 2 , STATE_TX_SCHEDULED = 3 }
enum  {
  REG_PAGE_REG = 0 , REG_SOFT_RESET = 1 , REG_VERSION = 2 , REG_RX_DATA_BUF_ADDR = 3 ,
  REG_RX_DATA_BUF_DATA = 4 , REG_TX_DATA_BUF_ADDR = 5 , REG_TX_DATA_BUF_DATA = 6 , REG_CAPTURE_RAM_ADDR = 7 ,
  REG_CAPTURE_RAM_DATA = 8 , REG_MCU_PROM_ADDR = 9 , REG_MCU_PROM_DATA = 10 , REG_RX_PACKET_DATA_FIFO_NUM_STORED = 11 ,
  REG_RX_PACKET_DATA_FIFO_ADDR_POINTER = 12 , REG_RX_PACKET_DATA_FIFO_STATUS = 13 , REG_RX_PACKET_DATA_FIFO_PAYLOAD_SIZE = 14 , REG_MBWSSF_MODEM_ENABLE = 15 ,
  REG_CONCENTRATOR_MODEM_ENABLE = 16 , REG_FSK_MODEM_ENABLE = 17 , REG_GLOBAL_EN = 18 , REG_CLK32M_EN = 19 ,
  REG_CLKHS_EN = 20 , REG_START_BIST0 = 21 , REG_START_BIST1 = 22 , REG_CLEAR_BIST0 = 23 ,
  REG_CLEAR_BIST1 = 24 , REG_BIST0_FINISHED = 25 , REG_BIST1_FINISHED = 26 , REG_MCU_AGC_PROG_RAM_BIST_STATUS = 27 ,
  REG_MCU_ARB_PROG_RAM_BIST_STATUS = 28 , REG_CAPTURE_RAM_BIST_STATUS = 29 , REG_CHAN_FIR_RAM0_BIST_STATUS = 30 , REG_CHAN_FIR_RAM1_BIST_STATUS = 31 ,
  REG_CORR0_RAM_BIST_STATUS = 32 , REG_CORR1_RAM_BIST_STATUS = 33 , REG_CORR2_RAM_BIST_STATUS = 34 , REG_CORR3_RAM_BIST_STATUS = 35 ,
  REG_CORR4_RAM_BIST_STATUS = 36 , REG_CORR5_RAM_BIST_STATUS = 37 , REG_CORR6_RAM_BIST_STATUS = 38 , REG_CORR7_RAM_BIST_STATUS = 39 ,
  REG_MODEM0_RAM0_BIST_STATUS = 40 , REG_MODEM1_RAM0_BIST_STATUS = 41 , REG_MODEM2_RAM0_BIST_STATUS = 42 , REG_MODEM3_RAM0_BIST_STATUS = 43 ,
  REG_MODEM4_RAM0_BIST_STATUS = 44 , REG_MODEM5_RAM0_BIST_STATUS = 45 , REG_MODEM6_RAM0_BIST_STATUS = 46 , REG_MODEM7_RAM0_BIST_STATUS = 47 ,
  REG_MODEM0_RAM1_BIST_STATUS = 48 , REG_MODEM1_RAM1_BIST_STATUS = 49 , REG_MODEM2_RAM1_BIST_STATUS = 50 , REG_MODEM3_RAM1_BIST_STATUS = 51 ,
  REG_MODEM4_RAM1_BIST_STATUS = 52 , REG_MODEM5_RAM1_BIST_STATUS = 53 , REG_MODEM6_RAM1_BIST_STATUS = 54 , REG_MODEM7_RAM1_BIST_STATUS = 55 ,
  REG_MODEM0_RAM2_BIST_STATUS = 56 , REG_MODEM1_RAM2_BIST_STATUS = 57 , REG_MODEM2_RAM2_BIST_STATUS = 58 , REG_MODEM3_RAM2_BIST_STATUS = 59 ,
  REG_MODEM4_RAM2_BIST_STATUS = 60 , REG_MODEM5_RAM2_BIST_STATUS = 61 , REG_MODEM6_RAM2_BIST_STATUS = 62 , REG_MODEM7_RAM2_BIST_STATUS = 63 ,
  REG_MODEM_MBWSSF_RAM0_BIST_STATUS = 64 , REG_MODEM_MBWSSF_RAM1_BIST_STATUS = 65 , REG_MODEM_MBWSSF_RAM2_BIST_STATUS = 66 , REG_MCU_AGC_DATA_RAM_BIST0_STATUS = 67 ,
  REG_MCU_AGC_DATA_RAM_BIST1_STATUS = 68 , REG_MCU_ARB_DATA_RAM_BIST0_STATUS = 69 , REG_MCU_ARB_DATA_RAM_BIST1_STATUS = 70 , REG_TX_TOP_RAM_BIST0_STATUS = 71 ,
  REG_TX_TOP_RAM_BIST1_STATUS = 72 , REG_DATA_MNGT_RAM_BIST0_STATUS = 73 , REG_DATA_MNGT_RAM_BIST1_STATUS = 74 , REG_GPIO_SELECT_INPUT = 75 ,
  REG_GPIO_SELECT_OUTPUT = 76 , REG_GPIO_MODE = 77 , REG_GPIO_PIN_REG_IN = 78 , REG_GPIO_PIN_REG_OUT = 79 ,
  REG_MCU_AGC_STATUS = 80 , REG_MCU_ARB_STATUS = 81 , REG_CHIP_ID = 82 , REG_EMERGENCY_FORCE_HOST_CTRL = 83 ,
  REG_RX_INVERT_IQ = 84 , REG_MODEM_INVERT_IQ = 85 , REG_MBWSSF_MODEM_INVERT_IQ = 86 , REG_RX_EDGE_SELECT = 87 ,
  REG_MISC_RADIO_EN = 88 , REG_FSK_MODEM_INVERT_IQ = 89 , REG_FILTER_GAIN = 90 , REG_RADIO_SELECT = 91 ,
  REG_IF_FREQ_0 = 92 , REG_IF_FREQ_1 = 93 , REG_IF_FREQ_2 = 94 , REG_IF_FREQ_3 = 95 ,
  REG_IF_FREQ_4 = 96 , REG_IF_FREQ_5 = 97 , REG_IF_FREQ_6 = 98 , REG_IF_FREQ_7 = 99 ,
  REG_IF_FREQ_8 = 100 , REG_IF_FREQ_9 = 101 , REG_CHANN_OVERRIDE_AGC_GAIN = 102 , REG_CHANN_AGC_GAIN = 103 ,
  REG_CORR0_DETECT_EN = 104 , REG_CORR1_DETECT_EN = 105 , REG_CORR2_DETECT_EN = 106 , REG_CORR3_DETECT_EN = 107 ,
  REG_CORR4_DETECT_EN = 108 , REG_CORR5_DETECT_EN = 109 , REG_CORR6_DETECT_EN = 110 , REG_CORR7_DETECT_EN = 111 ,
  REG_CORR_SAME_PEAKS_OPTION_SF6 = 112 , REG_CORR_SAME_PEAKS_OPTION_SF7 = 113 , REG_CORR_SAME_PEAKS_OPTION_SF8 = 114 , REG_CORR_SAME_PEAKS_OPTION_SF9 = 115 ,
  REG_CORR_SAME_PEAKS_OPTION_SF10 = 116 , REG_CORR_SAME_PEAKS_OPTION_SF11 = 117 , REG_CORR_SAME_PEAKS_OPTION_SF12 = 118 , REG_CORR_SIG_NOISE_RATIO_SF6 = 119 ,
  REG_CORR_SIG_NOISE_RATIO_SF7 = 120 , REG_CORR_SIG_NOISE_RATIO_SF8 = 121 , REG_CORR_SIG_NOISE_RATIO_SF9 = 122 , REG_CORR_SIG_NOISE_RATIO_SF10 = 123 ,
  REG_CORR_SIG_NOISE_RATIO_SF11 = 124 , REG_CORR_SIG_NOISE_RATIO_SF12 = 125 , REG_CORR_NUM_SAME_PEAK = 126 , REG_CORR_MAC_GAIN = 127 ,
  REG_ADJUST_MODEM_START_OFFSET_RDX4 = 128 , REG_ADJUST_MODEM_START_OFFSET_SF12_RDX4 = 129 , REG_DBG_CORR_SELECT_SF = 130 , REG_DBG_CORR_SELECT_CHANNEL = 131 ,
  REG_DBG_DETECT_CPT = 132 , REG_DBG_SYMB_CPT = 133 , REG_CHIRP_INVERT_RX = 134 , REG_DC_NOTCH_EN = 135 ,
  REG_IMPLICIT_CRC_EN = 136 , REG_IMPLICIT_CODING_RATE = 137 , REG_IMPLICIT_PAYLOAD_LENGHT = 138 , REG_FREQ_TO_TIME_INVERT = 139 ,
  REG_FREQ_TO_TIME_DRIFT = 140 , REG_PAYLOAD_FINE_TIMING_GAIN = 141 , REG_PREAMBLE_FINE_TIMING_GAIN = 142 , REG_TRACKING_INTEGRAL = 143 ,
  REG_FRAME_SYNCH_PEAK1_POS = 144 , REG_FRAME_SYNCH_PEAK2_POS = 145 , REG_PREAMBLE_SYMB1_NB = 146 , REG_FRAME_SYNCH_GAIN = 147 ,
  REG_SYNCH_DETECT_TH = 148 , REG_LLR_SCALE = 149 , REG_SNR_AVG_CST = 150 , REG_PPM_OFFSET = 151 ,
  REG_MAX_PAYLOAD_LEN = 152 , REG_ONLY_CRC_EN = 153 , REG_ZERO_PAD = 154 , REG_DEC_GAIN_OFFSET = 155 ,
  REG_CHAN_GAIN_OFFSET = 156 , REG_FORCE_HOST_RADIO_CTRL = 157 , REG_FORCE_HOST_FE_CTRL = 158 , REG_FORCE_DEC_FILTER_GAIN = 159 ,
  REG_MCU_RST_0 = 160 , REG_MCU_RST_1 = 161 , REG_MCU_SELECT_MUX_0 = 162 , REG_MCU_SELECT_MUX_1 = 163 ,
  REG_MCU_CORRUPTION_DETECTED_0 = 164 , REG_MCU_CORRUPTION_DETECTED_1 = 165 , REG_MCU_SELECT_EDGE_0 = 166 , REG_MCU_SELECT_EDGE_1 = 167 ,
  REG_CHANN_SELECT_RSSI = 168 , REG_RSSI_BB_DEFAULT_VALUE = 169 , REG_RSSI_DEC_DEFAULT_VALUE = 170 , REG_RSSI_CHANN_DEFAULT_VALUE = 171 ,
  REG_RSSI_BB_FILTER_ALPHA = 172 , REG_RSSI_DEC_FILTER_ALPHA = 173 , REG_RSSI_CHANN_FILTER_ALPHA = 174 , REG_IQ_MISMATCH_A_AMP_COEFF = 175 ,
  REG_IQ_MISMATCH_A_PHI_COEFF = 176 , REG_IQ_MISMATCH_B_AMP_COEFF = 177 , REG_IQ_MISMATCH_B_SEL_I = 178 , REG_IQ_MISMATCH_B_PHI_COEFF = 179 ,
  REG_TX_TRIG_IMMEDIATE = 180 , REG_TX_TRIG_DELAYED = 181 , REG_TX_TRIG_GPS = 182 , REG_TX_START_DELAY = 183 ,
  REG_TX_FRAME_SYNCH_PEAK1_POS = 184 , REG_TX_FRAME_SYNCH_PEAK2_POS = 185 , REG_TX_RAMP_DURATION = 186 , REG_TX_OFFSET_I = 187 ,
  REG_TX_OFFSET_Q = 188 , REG_TX_MODE = 189 , REG_TX_ZERO_PAD = 190 , REG_TX_EDGE_SELECT = 191 ,
  REG_TX_EDGE_SELECT_TOP = 192 , REG_TX_GAIN = 193 , REG_TX_CHIRP_LOW_PASS = 194 , REG_TX_FCC_WIDEBAND = 195 ,
  REG_TX_SWAP_IQ = 196 , REG_MBWSSF_IMPLICIT_HEADER = 197 , REG_MBWSSF_IMPLICIT_CRC_EN = 198 , REG_MBWSSF_IMPLICIT_CODING_RATE = 199 ,
  REG_MBWSSF_IMPLICIT_PAYLOAD_LENGHT = 200 , REG_MBWSSF_AGC_FREEZE_ON_DETECT = 201 , REG_MBWSSF_FRAME_SYNCH_PEAK1_POS = 202 , REG_MBWSSF_FRAME_SYNCH_PEAK2_POS = 203 ,
  REG_MBWSSF_PREAMBLE_SYMB1_NB = 204 , REG_MBWSSF_FRAME_SYNCH_GAIN = 205 , REG_MBWSSF_SYNCH_DETECT_TH = 206 , REG_MBWSSF_DETECT_MIN_SINGLE_PEAK = 207 ,
  REG_MBWSSF_DETECT_TRIG_SAME_PEAK_NB = 208 , REG_MBWSSF_FREQ_TO_TIME_INVERT = 209 , REG_MBWSSF_FREQ_TO_TIME_DRIFT = 210 , REG_MBWSSF_PPM_CORRECTION = 211 ,
  REG_MBWSSF_PAYLOAD_FINE_TIMING_GAIN = 212 , REG_MBWSSF_PREAMBLE_FINE_TIMING_GAIN = 213 , REG_MBWSSF_TRACKING_INTEGRAL = 214 , REG_MBWSSF_ZERO_PAD = 215 ,
  REG_MBWSSF_MODEM_BW = 216 , REG_MBWSSF_RADIO_SELECT = 217 , REG_MBWSSF_RX_CHIRP_INVERT = 218 , REG_MBWSSF_LLR_SCALE = 219 ,
  REG_MBWSSF_SNR_AVG_CST = 220 , REG_MBWSSF_PPM_OFFSET = 221 , REG_MBWSSF_RATE_SF = 222 , REG_MBWSSF_ONLY_CRC_EN = 223 ,
  REG_MBWSSF_MAX_PAYLOAD_LEN = 224 , REG_TX_STATUS = 225 , REG_FSK_CH_BW_EXPO = 226 , REG_FSK_RSSI_LENGTH = 227 ,
  REG_FSK_RX_INVERT = 228 , REG_FSK_PKT_MODE = 229 , REG_FSK_PSIZE = 230 , REG_FSK_CRC_EN = 231 ,
  REG_FSK_DCFREE_ENC = 232 , REG_FSK_CRC_IBM = 233 , REG_FSK_ERROR_OSR_TOL = 234 , REG_FSK_RADIO_SELECT = 235 ,
  REG_FSK_BR_RATIO = 236 , REG_FSK_REF_PATTERN_LSB = 237 , REG_FSK_REF_PATTERN_MSB = 238 , REG_FSK_PKT_LENGTH = 239 ,
  REG_FSK_TX_GAUSSIAN_EN = 240 , REG_FSK_TX_GAUSSIAN_SELECT_BT = 241 , REG_FSK_TX_PATTERN_EN = 242 , REG_FSK_TX_PREAMBLE_SEQ = 243 ,
  REG_FSK_TX_PSIZE = 244 , REG_FSK_NODE_ADRS = 245 , REG_FSK_BROADCAST = 246 , REG_FSK_AUTO_AFC_ON = 247 ,
  REG_FSK_PATTERN_TIMEOUT_CFG = 248 , REG_SPI_RADIO_A__DATA = 249 , REG_SPI_RADIO_A__DATA_READBACK = 250 , REG_SPI_RADIO_A__ADDR = 251 ,
  REG_SPI_RADIO_A__CS = 252 , REG_SPI_RADIO_B__DATA = 253 , REG_SPI_RADIO_B__DATA_READBACK = 254 , REG_SPI_RADIO_B__ADDR = 255 ,
  REG_SPI_RADIO_B__CS = 256 , REG_RADIO_A_EN = 257 , REG_RADIO_B_EN = 258 , REG_RADIO_RST = 259 ,
  REG_LNA_A_EN = 260 , REG_PA_A_EN = 261 , REG_LNA_B_EN = 262 , REG_PA_B_EN = 263 ,
  REG_PA_GAIN = 264 , REG_LNA_A_CTRL_LUT = 265 , REG_PA_A_CTRL_LUT = 266 , REG_LNA_B_CTRL_LUT = 267 ,
  REG_PA_B_CTRL_LUT = 268 , REG_CAPTURE_SOURCE = 269 , REG_CAPTURE_START = 270 , REG_CAPTURE_FORCE_TRIGGER = 271 ,
  REG_CAPTURE_WRAP = 272 , REG_CAPTURE_PERIOD = 273 , REG_MODEM_STATUS = 274 , REG_VALID_HEADER_COUNTER_0 = 275 ,
  REG_VALID_PACKET_COUNTER_0 = 276 , REG_VALID_HEADER_COUNTER_MBWSSF = 277 , REG_VALID_HEADER_COUNTER_FSK = 278 , REG_VALID_PACKET_COUNTER_MBWSSF = 279 ,
  REG_VALID_PACKET_COUNTER_FSK = 280 , REG_CHANN_RSSI = 281 , REG_BB_RSSI = 282 , REG_DEC_RSSI = 283 ,
  REG_DBG_MCU_DATA = 284 , REG_DBG_ARB_MCU_RAM_DATA = 285 , REG_DBG_AGC_MCU_RAM_DATA = 286 , REG_NEXT_PACKET_CNT = 287 ,
  REG_ADDR_CAPTURE_COUNT = 288 , REG_TIMESTAMP = 289 , REG_DBG_CHANN0_GAIN = 290 , REG_DBG_CHANN1_GAIN = 291 ,
  REG_DBG_CHANN2_GAIN = 292 , REG_DBG_CHANN3_GAIN = 293 , REG_DBG_CHANN4_GAIN = 294 , REG_DBG_CHANN5_GAIN = 295 ,
  REG_DBG_CHANN6_GAIN = 296 , REG_DBG_CHANN7_GAIN = 297 , REG_DBG_DEC_FILT_GAIN = 298 , REG_SPI_DATA_FIFO_PTR = 299 ,
  REG_PACKET_DATA_FIFO_PTR = 300 , REG_DBG_ARB_MCU_RAM_ADDR = 301 , REG_DBG_AGC_MCU_RAM_ADDR = 302 , REG_SPI_MASTER_CHIP_SELECT_POLARITY = 303 ,
  REG_SPI_MASTER_CPOL = 304 , REG_SPI_MASTER_CPHA = 305 , REG_SIG_GEN_ANALYSER_MUX_SEL = 306 , REG_SIG_GEN_EN = 307 ,
  REG_SIG_ANALYSER_EN = 308 , REG_SIG_ANALYSER_AVG_LEN = 309 , REG_SIG_ANALYSER_PRECISION = 310 , REG_SIG_ANALYSER_VALID_OUT = 311 ,
  REG_SIG_GEN_FREQ = 312 , REG_SIG_ANALYSER_FREQ = 313 , REG_SIG_ANALYSER_I_OUT = 314 , REG_SIG_ANALYSER_Q_OUT = 315 ,
  REG_GPS_EN = 316 , REG_GPS_POL = 317 , REG_SW_TEST_REG1 =318 , REG_SW_TEST_REG2 = 319 ,
  REG_SW_TEST_REG3 = 320 , REG_DATA_MNGT_STATUS = 321 , REG_DATA_MNGT_CPT_FRAME_ALLOCATED = 322 , REG_DATA_MNGT_CPT_FRAME_FINISHED = 323 ,
  REG_DATA_MNGT_CPT_FRAME_READEN = 324 , REG_TX_TRIG_ALL = 325 , NUM_TOTAL_REGS = 326
}

Protected Member Functions

void doIO ()
void beginTransaction ()
void endTransaction ()
virtual void regWrite (uint16_t reg, int32_t val)
virtual void regWriteBurst (uint16_t reg, const uint8_t *data, uint16_t size)
virtual int32_t regRead (uint16_t reg)
virtual void regReadBurst (uint16_t reg, uint8_t *data, uint16_t size)
void switchPage (uint8_t page)
virtual TxStatus_t getTxStatus ()

Protected Attributes

SPI * spi
int8_t pinCsn
int8_t pinReset
int8_t regpage
RadioPacket * txFrameToSend
RadioPacket * txFrameSent
uint8_t lastRxData [255+16]
uint8_t lastRxDataLen
struct { 
   bool   enabled:1 
   bool   txEnabled:1 
   uint32_t   freqHz 
   float   rssiOffset 
   uint32_t   txNotchFreqHz 
   Radio_t   type 
} rfChain [NUM_RF_CHAIN]
struct { 
   bool   enabled 
   uint8_t   rfChain 
   int32_t   rFreqHz 
   union { 
      struct { 
         uint8_t   sfMask 
      }   loraMulti
      struct { 
         uint8_t   bw 
         uint8_t   sf 
         bool   rxPpmOffset 
      }   loraStandalone
      struct { 
         uint8_t   bw 
         uint32_t   dr 
         uint8_t   syncwordSize 
         uint64_t   syncword 
      }   fskStandalone
   }   conf
} ifChain [NUM_IF_CHAIN]
int8_t calOffsetAI [8]
int8_t calOffsetAQ [8]
int8_t calOffsetBI [8]
int8_t calOffsetBQ [8]

Additional Inherited Members

Public Attributes inherited from PacketRadioChip
void(* onRxStarted )(void *, GPIOInterruptInfo_t *)
 수신이 시작될 때 호출될 콜백함수 포인터
void * ctxOnRxStarted
 onRxStarted 가 호출될 때 함께 전달될 context
void(* onRxDone )(void *, GPIOInterruptInfo_t *)
 수신이 완료될 때 호출될 콜백함수 포인터
void * ctxOnRxDone
 onRxDone 이 호출될 때 함께 전달될 context
void(* onTxDone )(void *, bool, GPIOInterruptInfo_t *)
 transmit() 후, 송신이 완료될 때 호출될 콜백함수 포인터
void * ctxOnTxDone
 onTxDone 이 호출될 때 함께 전달될 context
void(* onChannelBusy )(void *, GPIOInterruptInfo_t *)
 cca() 시 채널이 혼잡할 때 호출될 콜백함수 포인터
void * ctxOnChannelBusy
 onChannelBusy 가 호출될 때 함께 전달될 context
int16_t dBccaThreshold = -65
 cca() 시 채널이 혼잡하다고 판단하기 위한 에너지 레벨을 설정합니다. (단위: dB, 기본값: -65)

Detailed Description

저전력 multi-band LoRaTM 및 FSK 무선 통신을 지원하는 Semtech의 SX1301 radio concentrator 을 지원합니다.

Rx

SX1301에서는 8개의 multi datarate LoRaTM interface, 1개의 LoRaTM standalone interface, 그리고 1개의 FSK standalone interface 를 지원합니다. 이를 설정하기 위해서는 SX1301Chip::configureRf(), 및 SX1301Chip::configureRxIf() 를 사용합니다.

위 예제는 SX1301에 SX1257 2개가 연결된 하드웨어 구성에서 사용할 수 있으며, 다음과 같이 수신 설정이 됩니다.

Interface #Interface TypeListening frequencyRx bandwidth
0Multi datarate LoRaTM interface921.9 MHz125 kHz
1Multi datarate LoRaTM interface922.1 MHz125 kHz
2Multi datarate LoRaTM interface922.3 MHz125 kHz
3Multi datarate LoRaTM interface922.5 MHz125 kHz
4Multi datarate LoRaTM interface922.7 MHz125 kHz
5Multi datarate LoRaTM interface922.9 MHz125 kHz
6Multi datarate LoRaTM interface923.1 MHz125 kHz
7Multi datarate LoRaTM interface923.3 MHz125 kHz
8LoRaTM standalone interface923.3 MHz250 kHz
9FSK standalone interface921.7 MHz250 kHz

패킷 수신시, PacketRadioChip::onRxDone() 에서 지정한 콜백함수가 호출됩니다. 콜백함수에서 PacketRadioChip::readFrame() 을 통해 수신한 패킷을 읽을 수 있습니다.

Tx

SX1301에서 패킷을 송신하기 위해서는 PacketRadioChip::transmit() 을 이용하되, 인자 RadioPacket 에 modulation 등 원하는 파라미터를 설정해야 합니다.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum
Enumerator
ERROR_TX_GAIN_DIG 

Digital gain 설정 오류

ERROR_TX_GAIN_DAC 

DAC gain 설정 오류

ERROR_TX_GAIN_MIX 

Mixer gain 설정 오류

ERROR_TX_GAIN_PA 

PA gain 설정 오류

379 {
380 ERROR_TX_GAIN_DIG = -100,
381 ERROR_TX_GAIN_DAC = -101,
382 ERROR_TX_GAIN_MIX = -102,
383 ERROR_TX_GAIN_PA = -103,
384 };
SX1301Chip::ERROR_TX_GAIN_MIX
@ ERROR_TX_GAIN_MIX
Definition SX1301Chip.hpp:382
SX1301Chip::ERROR_TX_GAIN_DAC
@ ERROR_TX_GAIN_DAC
Definition SX1301Chip.hpp:381
SX1301Chip::ERROR_TX_GAIN_PA
@ ERROR_TX_GAIN_PA
Definition SX1301Chip.hpp:383
SX1301Chip::ERROR_TX_GAIN_DIG
@ ERROR_TX_GAIN_DIG
Definition SX1301Chip.hpp:380

◆ anonymous enum

anonymous enum
protected
499 {
500 REG_PAGE_REG = 0,
501 REG_SOFT_RESET = 1,
502 REG_VERSION = 2,
503 REG_RX_DATA_BUF_ADDR = 3,
504 REG_RX_DATA_BUF_DATA = 4,
505 REG_TX_DATA_BUF_ADDR = 5,
506 REG_TX_DATA_BUF_DATA = 6,
507 REG_CAPTURE_RAM_ADDR = 7,
508 REG_CAPTURE_RAM_DATA = 8,
509 REG_MCU_PROM_ADDR = 9,
510 REG_MCU_PROM_DATA = 10,
511 REG_RX_PACKET_DATA_FIFO_NUM_STORED = 11,
512 REG_RX_PACKET_DATA_FIFO_ADDR_POINTER = 12,
513 REG_RX_PACKET_DATA_FIFO_STATUS = 13,
514 REG_RX_PACKET_DATA_FIFO_PAYLOAD_SIZE = 14,
515 REG_MBWSSF_MODEM_ENABLE = 15,
516 REG_CONCENTRATOR_MODEM_ENABLE = 16,
517 REG_FSK_MODEM_ENABLE = 17,
518 REG_GLOBAL_EN = 18,
519 REG_CLK32M_EN = 19,
520 REG_CLKHS_EN = 20,
521 REG_START_BIST0 = 21,
522 REG_START_BIST1 = 22,
523 REG_CLEAR_BIST0 = 23,
524 REG_CLEAR_BIST1 = 24,
525 REG_BIST0_FINISHED = 25,
526 REG_BIST1_FINISHED = 26,
527 REG_MCU_AGC_PROG_RAM_BIST_STATUS = 27,
528 REG_MCU_ARB_PROG_RAM_BIST_STATUS = 28,
529 REG_CAPTURE_RAM_BIST_STATUS = 29,
530 REG_CHAN_FIR_RAM0_BIST_STATUS = 30,
531 REG_CHAN_FIR_RAM1_BIST_STATUS = 31,
532 REG_CORR0_RAM_BIST_STATUS = 32,
533 REG_CORR1_RAM_BIST_STATUS = 33,
534 REG_CORR2_RAM_BIST_STATUS = 34,
535 REG_CORR3_RAM_BIST_STATUS = 35,
536 REG_CORR4_RAM_BIST_STATUS = 36,
537 REG_CORR5_RAM_BIST_STATUS = 37,
538 REG_CORR6_RAM_BIST_STATUS = 38,
539 REG_CORR7_RAM_BIST_STATUS = 39,
540 REG_MODEM0_RAM0_BIST_STATUS = 40,
541 REG_MODEM1_RAM0_BIST_STATUS = 41,
542 REG_MODEM2_RAM0_BIST_STATUS = 42,
543 REG_MODEM3_RAM0_BIST_STATUS = 43,
544 REG_MODEM4_RAM0_BIST_STATUS = 44,
545 REG_MODEM5_RAM0_BIST_STATUS = 45,
546 REG_MODEM6_RAM0_BIST_STATUS = 46,
547 REG_MODEM7_RAM0_BIST_STATUS = 47,
548 REG_MODEM0_RAM1_BIST_STATUS = 48,
549 REG_MODEM1_RAM1_BIST_STATUS = 49,
550 REG_MODEM2_RAM1_BIST_STATUS = 50,
551 REG_MODEM3_RAM1_BIST_STATUS = 51,
552 REG_MODEM4_RAM1_BIST_STATUS = 52,
553 REG_MODEM5_RAM1_BIST_STATUS = 53,
554 REG_MODEM6_RAM1_BIST_STATUS = 54,
555 REG_MODEM7_RAM1_BIST_STATUS = 55,
556 REG_MODEM0_RAM2_BIST_STATUS = 56,
557 REG_MODEM1_RAM2_BIST_STATUS = 57,
558 REG_MODEM2_RAM2_BIST_STATUS = 58,
559 REG_MODEM3_RAM2_BIST_STATUS = 59,
560 REG_MODEM4_RAM2_BIST_STATUS = 60,
561 REG_MODEM5_RAM2_BIST_STATUS = 61,
562 REG_MODEM6_RAM2_BIST_STATUS = 62,
563 REG_MODEM7_RAM2_BIST_STATUS = 63,
564 REG_MODEM_MBWSSF_RAM0_BIST_STATUS = 64,
565 REG_MODEM_MBWSSF_RAM1_BIST_STATUS = 65,
566 REG_MODEM_MBWSSF_RAM2_BIST_STATUS = 66,
567 REG_MCU_AGC_DATA_RAM_BIST0_STATUS = 67,
568 REG_MCU_AGC_DATA_RAM_BIST1_STATUS = 68,
569 REG_MCU_ARB_DATA_RAM_BIST0_STATUS = 69,
570 REG_MCU_ARB_DATA_RAM_BIST1_STATUS = 70,
571 REG_TX_TOP_RAM_BIST0_STATUS = 71,
572 REG_TX_TOP_RAM_BIST1_STATUS = 72,
573 REG_DATA_MNGT_RAM_BIST0_STATUS = 73,
574 REG_DATA_MNGT_RAM_BIST1_STATUS = 74,
575 REG_GPIO_SELECT_INPUT = 75,
576 REG_GPIO_SELECT_OUTPUT = 76,
577 REG_GPIO_MODE = 77,
578 REG_GPIO_PIN_REG_IN = 78,
579 REG_GPIO_PIN_REG_OUT = 79,
580 REG_MCU_AGC_STATUS = 80,
581 REG_MCU_ARB_STATUS = 81,
582 REG_CHIP_ID = 82,
583 REG_EMERGENCY_FORCE_HOST_CTRL = 83,
584 REG_RX_INVERT_IQ = 84,
585 REG_MODEM_INVERT_IQ = 85,
586 REG_MBWSSF_MODEM_INVERT_IQ = 86,
587 REG_RX_EDGE_SELECT = 87,
588 REG_MISC_RADIO_EN = 88,
589 REG_FSK_MODEM_INVERT_IQ = 89,
590 REG_FILTER_GAIN = 90,
591 REG_RADIO_SELECT = 91,
592 REG_IF_FREQ_0 = 92,
593 REG_IF_FREQ_1 = 93,
594 REG_IF_FREQ_2 = 94,
595 REG_IF_FREQ_3 = 95,
596 REG_IF_FREQ_4 = 96,
597 REG_IF_FREQ_5 = 97,
598 REG_IF_FREQ_6 = 98,
599 REG_IF_FREQ_7 = 99,
600 REG_IF_FREQ_8 = 100,
601 REG_IF_FREQ_9 = 101,
602 REG_CHANN_OVERRIDE_AGC_GAIN = 102,
603 REG_CHANN_AGC_GAIN = 103,
604 REG_CORR0_DETECT_EN = 104,
605 REG_CORR1_DETECT_EN = 105,
606 REG_CORR2_DETECT_EN = 106,
607 REG_CORR3_DETECT_EN = 107,
608 REG_CORR4_DETECT_EN = 108,
609 REG_CORR5_DETECT_EN = 109,
610 REG_CORR6_DETECT_EN = 110,
611 REG_CORR7_DETECT_EN = 111,
612 REG_CORR_SAME_PEAKS_OPTION_SF6 = 112,
613 REG_CORR_SAME_PEAKS_OPTION_SF7 = 113,
614 REG_CORR_SAME_PEAKS_OPTION_SF8 = 114,
615 REG_CORR_SAME_PEAKS_OPTION_SF9 = 115,
616 REG_CORR_SAME_PEAKS_OPTION_SF10 = 116,
617 REG_CORR_SAME_PEAKS_OPTION_SF11 = 117,
618 REG_CORR_SAME_PEAKS_OPTION_SF12 = 118,
619 REG_CORR_SIG_NOISE_RATIO_SF6 = 119,
620 REG_CORR_SIG_NOISE_RATIO_SF7 = 120,
621 REG_CORR_SIG_NOISE_RATIO_SF8 = 121,
622 REG_CORR_SIG_NOISE_RATIO_SF9 = 122,
623 REG_CORR_SIG_NOISE_RATIO_SF10 = 123,
624 REG_CORR_SIG_NOISE_RATIO_SF11 = 124,
625 REG_CORR_SIG_NOISE_RATIO_SF12 = 125,
626 REG_CORR_NUM_SAME_PEAK = 126,
627 REG_CORR_MAC_GAIN = 127,
628 REG_ADJUST_MODEM_START_OFFSET_RDX4 = 128,
629 REG_ADJUST_MODEM_START_OFFSET_SF12_RDX4 = 129,
630 REG_DBG_CORR_SELECT_SF = 130,
631 REG_DBG_CORR_SELECT_CHANNEL = 131,
632 REG_DBG_DETECT_CPT = 132,
633 REG_DBG_SYMB_CPT = 133,
634 REG_CHIRP_INVERT_RX = 134,
635 REG_DC_NOTCH_EN = 135,
636 REG_IMPLICIT_CRC_EN = 136,
637 REG_IMPLICIT_CODING_RATE = 137,
638 REG_IMPLICIT_PAYLOAD_LENGHT = 138,
639 REG_FREQ_TO_TIME_INVERT = 139,
640 REG_FREQ_TO_TIME_DRIFT = 140,
641 REG_PAYLOAD_FINE_TIMING_GAIN = 141,
642 REG_PREAMBLE_FINE_TIMING_GAIN = 142,
643 REG_TRACKING_INTEGRAL = 143,
644 REG_FRAME_SYNCH_PEAK1_POS = 144,
645 REG_FRAME_SYNCH_PEAK2_POS = 145,
646 REG_PREAMBLE_SYMB1_NB = 146,
647 REG_FRAME_SYNCH_GAIN = 147,
648 REG_SYNCH_DETECT_TH = 148,
649 REG_LLR_SCALE = 149,
650 REG_SNR_AVG_CST = 150,
651 REG_PPM_OFFSET = 151,
652 REG_MAX_PAYLOAD_LEN = 152,
653 REG_ONLY_CRC_EN = 153,
654 REG_ZERO_PAD = 154,
655 REG_DEC_GAIN_OFFSET = 155,
656 REG_CHAN_GAIN_OFFSET = 156,
657 REG_FORCE_HOST_RADIO_CTRL = 157,
658 REG_FORCE_HOST_FE_CTRL = 158,
659 REG_FORCE_DEC_FILTER_GAIN = 159,
660 REG_MCU_RST_0 = 160,
661 REG_MCU_RST_1 = 161,
662 REG_MCU_SELECT_MUX_0 = 162,
663 REG_MCU_SELECT_MUX_1 = 163,
664 REG_MCU_CORRUPTION_DETECTED_0 = 164,
665 REG_MCU_CORRUPTION_DETECTED_1 = 165,
666 REG_MCU_SELECT_EDGE_0 = 166,
667 REG_MCU_SELECT_EDGE_1 = 167,
668 REG_CHANN_SELECT_RSSI = 168,
669 REG_RSSI_BB_DEFAULT_VALUE = 169,
670 REG_RSSI_DEC_DEFAULT_VALUE = 170,
671 REG_RSSI_CHANN_DEFAULT_VALUE = 171,
672 REG_RSSI_BB_FILTER_ALPHA = 172,
673 REG_RSSI_DEC_FILTER_ALPHA = 173,
674 REG_RSSI_CHANN_FILTER_ALPHA = 174,
675 REG_IQ_MISMATCH_A_AMP_COEFF = 175,
676 REG_IQ_MISMATCH_A_PHI_COEFF = 176,
677 REG_IQ_MISMATCH_B_AMP_COEFF = 177,
678 REG_IQ_MISMATCH_B_SEL_I = 178,
679 REG_IQ_MISMATCH_B_PHI_COEFF = 179,
680 REG_TX_TRIG_IMMEDIATE = 180,
681 REG_TX_TRIG_DELAYED = 181,
682 REG_TX_TRIG_GPS = 182,
683 REG_TX_START_DELAY = 183,
684 REG_TX_FRAME_SYNCH_PEAK1_POS = 184,
685 REG_TX_FRAME_SYNCH_PEAK2_POS = 185,
686 REG_TX_RAMP_DURATION = 186,
687 REG_TX_OFFSET_I = 187,
688 REG_TX_OFFSET_Q = 188,
689 REG_TX_MODE = 189,
690 REG_TX_ZERO_PAD = 190,
691 REG_TX_EDGE_SELECT = 191,
692 REG_TX_EDGE_SELECT_TOP = 192,
693 REG_TX_GAIN = 193,
694 REG_TX_CHIRP_LOW_PASS = 194,
695 REG_TX_FCC_WIDEBAND = 195,
696 REG_TX_SWAP_IQ = 196,
697 REG_MBWSSF_IMPLICIT_HEADER = 197,
698 REG_MBWSSF_IMPLICIT_CRC_EN = 198,
699 REG_MBWSSF_IMPLICIT_CODING_RATE = 199,
700 REG_MBWSSF_IMPLICIT_PAYLOAD_LENGHT = 200,
701 REG_MBWSSF_AGC_FREEZE_ON_DETECT = 201,
702 REG_MBWSSF_FRAME_SYNCH_PEAK1_POS = 202,
703 REG_MBWSSF_FRAME_SYNCH_PEAK2_POS = 203,
704 REG_MBWSSF_PREAMBLE_SYMB1_NB = 204,
705 REG_MBWSSF_FRAME_SYNCH_GAIN = 205,
706 REG_MBWSSF_SYNCH_DETECT_TH = 206,
707 REG_MBWSSF_DETECT_MIN_SINGLE_PEAK = 207,
708 REG_MBWSSF_DETECT_TRIG_SAME_PEAK_NB = 208,
709 REG_MBWSSF_FREQ_TO_TIME_INVERT = 209,
710 REG_MBWSSF_FREQ_TO_TIME_DRIFT = 210,
711 REG_MBWSSF_PPM_CORRECTION = 211,
712 REG_MBWSSF_PAYLOAD_FINE_TIMING_GAIN = 212,
713 REG_MBWSSF_PREAMBLE_FINE_TIMING_GAIN = 213,
714 REG_MBWSSF_TRACKING_INTEGRAL = 214,
715 REG_MBWSSF_ZERO_PAD = 215,
716 REG_MBWSSF_MODEM_BW = 216,
717 REG_MBWSSF_RADIO_SELECT = 217,
718 REG_MBWSSF_RX_CHIRP_INVERT = 218,
719 REG_MBWSSF_LLR_SCALE = 219,
720 REG_MBWSSF_SNR_AVG_CST = 220,
721 REG_MBWSSF_PPM_OFFSET = 221,
722 REG_MBWSSF_RATE_SF = 222,
723 REG_MBWSSF_ONLY_CRC_EN = 223,
724 REG_MBWSSF_MAX_PAYLOAD_LEN = 224,
725 REG_TX_STATUS = 225,
726 REG_FSK_CH_BW_EXPO = 226,
727 REG_FSK_RSSI_LENGTH = 227,
728 REG_FSK_RX_INVERT = 228,
729 REG_FSK_PKT_MODE = 229,
730 REG_FSK_PSIZE = 230,
731 REG_FSK_CRC_EN = 231,
732 REG_FSK_DCFREE_ENC = 232,
733 REG_FSK_CRC_IBM = 233,
734 REG_FSK_ERROR_OSR_TOL = 234,
735 REG_FSK_RADIO_SELECT = 235,
736 REG_FSK_BR_RATIO = 236,
737 REG_FSK_REF_PATTERN_LSB = 237,
738 REG_FSK_REF_PATTERN_MSB = 238,
739 REG_FSK_PKT_LENGTH = 239,
740 REG_FSK_TX_GAUSSIAN_EN = 240,
741 REG_FSK_TX_GAUSSIAN_SELECT_BT = 241,
742 REG_FSK_TX_PATTERN_EN = 242,
743 REG_FSK_TX_PREAMBLE_SEQ = 243,
744 REG_FSK_TX_PSIZE = 244,
745 REG_FSK_NODE_ADRS = 245,
746 REG_FSK_BROADCAST = 246,
747 REG_FSK_AUTO_AFC_ON = 247,
748 REG_FSK_PATTERN_TIMEOUT_CFG = 248,
749 REG_SPI_RADIO_A__DATA = 249,
750 REG_SPI_RADIO_A__DATA_READBACK = 250,
751 REG_SPI_RADIO_A__ADDR = 251,
752 REG_SPI_RADIO_A__CS = 252,
753 REG_SPI_RADIO_B__DATA = 253,
754 REG_SPI_RADIO_B__DATA_READBACK = 254,
755 REG_SPI_RADIO_B__ADDR = 255,
756 REG_SPI_RADIO_B__CS = 256,
757 REG_RADIO_A_EN = 257,
758 REG_RADIO_B_EN = 258,
759 REG_RADIO_RST = 259,
760 REG_LNA_A_EN = 260,
761 REG_PA_A_EN = 261,
762 REG_LNA_B_EN = 262,
763 REG_PA_B_EN = 263,
764 REG_PA_GAIN = 264,
765 REG_LNA_A_CTRL_LUT = 265,
766 REG_PA_A_CTRL_LUT = 266,
767 REG_LNA_B_CTRL_LUT = 267,
768 REG_PA_B_CTRL_LUT = 268,
769 REG_CAPTURE_SOURCE = 269,
770 REG_CAPTURE_START = 270,
771 REG_CAPTURE_FORCE_TRIGGER = 271,
772 REG_CAPTURE_WRAP = 272,
773 REG_CAPTURE_PERIOD = 273,
774 REG_MODEM_STATUS = 274,
775 REG_VALID_HEADER_COUNTER_0 = 275,
776 REG_VALID_PACKET_COUNTER_0 = 276,
777 REG_VALID_HEADER_COUNTER_MBWSSF = 277,
778 REG_VALID_HEADER_COUNTER_FSK = 278,
779 REG_VALID_PACKET_COUNTER_MBWSSF = 279,
780 REG_VALID_PACKET_COUNTER_FSK = 280,
781 REG_CHANN_RSSI = 281,
782 REG_BB_RSSI = 282,
783 REG_DEC_RSSI = 283,
784 REG_DBG_MCU_DATA = 284,
785 REG_DBG_ARB_MCU_RAM_DATA = 285,
786 REG_DBG_AGC_MCU_RAM_DATA = 286,
787 REG_NEXT_PACKET_CNT = 287,
788 REG_ADDR_CAPTURE_COUNT = 288,
789 REG_TIMESTAMP = 289,
790 REG_DBG_CHANN0_GAIN = 290,
791 REG_DBG_CHANN1_GAIN = 291,
792 REG_DBG_CHANN2_GAIN = 292,
793 REG_DBG_CHANN3_GAIN = 293,
794 REG_DBG_CHANN4_GAIN = 294,
795 REG_DBG_CHANN5_GAIN = 295,
796 REG_DBG_CHANN6_GAIN = 296,
797 REG_DBG_CHANN7_GAIN = 297,
798 REG_DBG_DEC_FILT_GAIN = 298,
799 REG_SPI_DATA_FIFO_PTR = 299,
800 REG_PACKET_DATA_FIFO_PTR = 300,
801 REG_DBG_ARB_MCU_RAM_ADDR = 301,
802 REG_DBG_AGC_MCU_RAM_ADDR = 302,
803 REG_SPI_MASTER_CHIP_SELECT_POLARITY = 303,
804 REG_SPI_MASTER_CPOL = 304,
805 REG_SPI_MASTER_CPHA = 305,
806 REG_SIG_GEN_ANALYSER_MUX_SEL = 306,
807 REG_SIG_GEN_EN = 307,
808 REG_SIG_ANALYSER_EN = 308,
809 REG_SIG_ANALYSER_AVG_LEN = 309,
810 REG_SIG_ANALYSER_PRECISION = 310,
811 REG_SIG_ANALYSER_VALID_OUT = 311,
812 REG_SIG_GEN_FREQ = 312,
813 REG_SIG_ANALYSER_FREQ = 313,
814 REG_SIG_ANALYSER_I_OUT = 314,
815 REG_SIG_ANALYSER_Q_OUT = 315,
816 REG_GPS_EN = 316,
817 REG_GPS_POL = 317,
818 REG_SW_TEST_REG1 =318,
819 REG_SW_TEST_REG2 = 319,
820 REG_SW_TEST_REG3 = 320,
821 REG_DATA_MNGT_STATUS = 321,
822 REG_DATA_MNGT_CPT_FRAME_ALLOCATED = 322,
823 REG_DATA_MNGT_CPT_FRAME_FINISHED = 323,
824 REG_DATA_MNGT_CPT_FRAME_READEN = 324,
825 REG_TX_TRIG_ALL = 325,
826 NUM_TOTAL_REGS = 326,
827 };

◆ anonymous enum

anonymous enum
422 {
423 MCU_AGC_FW_BYTE = 8192,
424 MCU_ARB_FW_BYTE = 8192,
425 };

◆ anonymous enum

anonymous enum
267 {
268 BW_UNDEFINED = 0,
269 BW_500kHz = 1,
270 BW_250kHz = 2,
271 BW_125kHz = 3,
272 BW_62_5kHz = 4,
273 BW_31_2kHz = 5,
274 BW_15_6kHz = 6,
275 BW_7_8kHz = 7,
276 };

◆ anonymous enum

anonymous enum
278 {
279 DR_UNDEFINED = 0,
280 DR_LORA_SF7 = (1 << 1),
281 DR_LORA_SF8 = (1 << 2),
282 DR_LORA_SF9 = (1 << 3),
283 DR_LORA_SF10 = (1 << 4),
284 DR_LORA_SF11 = (1 << 5),
285 DR_LORA_SF12 = (1 << 6),
286 DR_LORA_MULTI = 0x7E,
287 DR_FSK_MIN = 500,
288 DR_FSK_MAX = 250000,
289 };

◆ anonymous enum

anonymous enum
Enumerator
ERROR_IF_FREQ_TOO_HIGH 

주파수가 너무 높음

ERROR_IF_FREQ_TOO_LOW 

주파수가 너무 낮음

ERROR_IF_BANDWIDTH_NOT_SUPPORTED 

미지원 대역폭

ERROR_IF_DATARATE_NOT_SUPPORTED 

미지원 data rate

336 {
337 ERROR_IF_FREQ_TOO_HIGH = -100,
338 ERROR_IF_FREQ_TOO_LOW = -101,
339 ERROR_IF_BANDWIDTH_NOT_SUPPORTED = -102,
340 ERROR_IF_DATARATE_NOT_SUPPORTED = -103,
341 };
SX1301Chip::ERROR_IF_FREQ_TOO_HIGH
@ ERROR_IF_FREQ_TOO_HIGH
Definition SX1301Chip.hpp:337
SX1301Chip::ERROR_IF_FREQ_TOO_LOW
@ ERROR_IF_FREQ_TOO_LOW
Definition SX1301Chip.hpp:338
SX1301Chip::ERROR_IF_BANDWIDTH_NOT_SUPPORTED
@ ERROR_IF_BANDWIDTH_NOT_SUPPORTED
Definition SX1301Chip.hpp:339
SX1301Chip::ERROR_IF_DATARATE_NOT_SUPPORTED
@ ERROR_IF_DATARATE_NOT_SUPPORTED
Definition SX1301Chip.hpp:340

◆ anonymous enum

anonymous enum
Enumerator
NUM_RF_CHAIN 

Number of RF interfaces

NUM_IF_CHAIN 

Number of Rx interfaces

NUM_TX_GAIN 

Size of Tx lookup table

IF_INDEX_LORA_STANDALONE 

LoRa standalone interface

IF_INDEX_FSK_STANDALONE 

FSK standalone interface

233 {
234 NUM_RF_CHAIN = 2,
235 NUM_IF_CHAIN = 10,
236 NUM_TX_GAIN = 16,
237 IF_INDEX_LORA_STANDALONE = 8,
238 IF_INDEX_FSK_STANDALONE = 9,
239 };
SX1301Chip::NUM_RF_CHAIN
@ NUM_RF_CHAIN
Definition SX1301Chip.hpp:234
SX1301Chip::IF_INDEX_FSK_STANDALONE
@ IF_INDEX_FSK_STANDALONE
Definition SX1301Chip.hpp:238
SX1301Chip::NUM_TX_GAIN
@ NUM_TX_GAIN
Definition SX1301Chip.hpp:236
SX1301Chip::NUM_IF_CHAIN
@ NUM_IF_CHAIN
Definition SX1301Chip.hpp:235
SX1301Chip::IF_INDEX_LORA_STANDALONE
@ IF_INDEX_LORA_STANDALONE
Definition SX1301Chip.hpp:237

◆ Radio_t

enum SX1301Chip::Radio_t
Enumerator
RADIO_TYPE_SX1255 

SX1255

RADIO_TYPE_SX1257 

SX1257

227 {
228 RADIO_TYPE_NONE = 0,
229 RADIO_TYPE_SX1255 = 1,
230 RADIO_TYPE_SX1257 = 2,
231 } Radio_t;
SX1301Chip::Radio_t
Radio_t
Definition SX1301Chip.hpp:227
SX1301Chip::RADIO_TYPE_SX1257
@ RADIO_TYPE_SX1257
Definition SX1301Chip.hpp:230
SX1301Chip::RADIO_TYPE_SX1255
@ RADIO_TYPE_SX1255
Definition SX1301Chip.hpp:229

◆ TxStatus_t

enum SX1301Chip::TxStatus_t
protected
491 {
492 STATE_TX_OFF = 0,
493 STATE_TX_FREE = 1,
494 STATE_TX_EMITTING = 2,
495 STATE_TX_SCHEDULED = 3,
496 } TxStatus_t;

Member Function Documentation

◆ begin()

error_t SX1301Chip::begin ( )
virtual

SX1301 의 동작을 시작합니다.

Implements PacketRadioChip.

◆ bufferIsEmpty()

bool SX1301Chip::bufferIsEmpty ( )
virtual

Implements PacketRadioChip.

◆ cca()

bool SX1301Chip::cca ( )
overridevirtual

채널이 혼잡한지 아닌지 검사합니다.

채널이 혼잡하다고 감지되는 순간, onChannelBusy 가 가리키는 콜백함수가 호출됩니다.

Implements PacketRadioChip.

◆ configureRf()

error_t SX1301Chip::configureRf ( uint8_t index,
bool enable,
bool txEnable,
uint32_t freqHz,
float rssiOffset = -166.0,
Radio_t type = RADIO_TYPE_SX1257,
uint32_t txNotchFreqHz = 0 )

RF interface를 설정합니다.

Parameters
indexRF interface의 index (0~1)
enableRF interface의 활성화 여부
txEnableRF interface에서의 Tx 활성화 여부
freqHzRF interface에 설정할 중심 주파수 (단위: Hz)
rssiOffsetRSSI 교정 offset (기본 값: -166)
typeRF chain의 타입 (기본 값: SX1301Chip::RADIO_TYPE_SX1257)
txNotchFreqHzTx notch filter frequency (126kHz ~ 250kHz) for SX1301AP2 (FPGA)
Returns
  • ERROR_SUCCESS : 설정 성공.
  • ERROR_FAIL : 칩이 이미 시작되어 설정할 수 없음
  • ERROR_INVALID_ARGS : index, type 등 파라미터가 유효하지 않음

◆ configureRxIf()

error_t SX1301Chip::configureRxIf ( uint8_t index,
uint8_t rfChainIndex,
bool enable,
int32_t rFreqHz,
uint8_t bandwidth = BW_UNDEFINED,
uint32_t datarate = DR_UNDEFINED,
uint8_t fskSyncwordSize = 3,
uint64_t fskSyncword = 0xC194C1 )

Rx interface를 설정합니다.

Parameters
indexIF chain의 index (0~7: multi LoRa, 8: SX1301Chip::IF_INDEX_LORA_STANDALONE, 9: SX1301Chip::IF_INDEX_FSK_STANDALONE)
rfChainIndex사용할 RF chain의 index
enableIF chain의 활성화 여부
rFreqHz수신 대기할 주파수. RF chain의 중심 주파수 기준의 상대 주파수
bandwidth수신 대기할 bandwidth. Default는 SX1301Chip::BW_UNDEFINED 이며, LoRa interface 에서는 125kHz, FSK standalone interface 에서는 250kHz로 설정됩니다.
datarate수신 대기할 datarate. Multi channel LoRa interface 에서는 SF7으로 고정되고, LoRa standalone interface 에서는 SX1301Chip::DR_LORA_SF7 ~ SX1301Chip::DR_LORA_SF12 사이의 값으로 설정 가능합니다. FSK standalone interface인 경우, 500 ~ 250000 사이의 값이어야 합니다. Default는 SX1301Chip::DR_UNDEFINED 이며, 이는 LoRa standalone interface에서는 SX1301Chip::DR_LORA_SF7, FSK standalone 인 경우, 50000 으로 설정됩니다.
fskSyncwordSizeFSK syncword의 크기 (# of bytes). Default는 3.
fskSyncwordFSK syncword (aligned right, MSBit first). Default는 0xC194C1.
Returns

◆ configureTxGain()

error_t SX1301Chip::configureTxGain ( uint8_t index,
uint8_t digGain,
uint8_t paGain,
uint8_t dacGain,
uint8_t mixGain,
int8_t dBm )

Tx Gain look up table을 설정합니다.

Parameters
indexLook up table index (0~15)
digGainDigital gain (2-bits)
paGain외부 PA (2-bits)
dacGainRadio DAC (2-bits)
mixGainRadio mixer (2-bits)
dBm보드 커넥터에서 측정된 Tx power (dBm 단위)
Returns

◆ flushBuffer()

void SX1301Chip::flushBuffer ( )
virtual

Implements PacketRadioChip.

◆ getChannel() [1/2]

uint32_t SX1301Chip::getChannel ( )
virtual

현재 설정된 채널을 반환합니다.

Implements PacketRadioChip.

◆ getChannel() [2/2]

uint32_t SX1301Chip::getChannel ( uint8_t index)

Rx interface 별 설정된 주파수를 가져옵니다.

Parameters
indexRx interface의 index (0~9)
Returns
index 가 유효하고, 활성화된 interface 인 경우 주파수. (단위: Hz) 그렇지 않은 경우 0.

◆ getTxPower()

int8_t SX1301Chip::getTxPower ( )
virtual

현재 설정된 송신 출력을 반환합니다.

Returns
송신 출력 (단위: dBm)

Implements PacketRadioChip.

◆ readFrame()

error_t SX1301Chip::readFrame ( RadioPacket * frame)
virtual

수신 버퍼에서 프레임을 읽습니다.

Returns
  • ERROR_SUCCESS : 성공
  • ERROR_FAIL : 실패 (수신한 프레임이 없음)
  • ERROR_INVALID_ARGS : frame 이 NULL 이거나, frame 내부 버퍼가 충분히 크지 않아서 실패

Implements PacketRadioChip.

◆ setBandwidth()

error_t SX1301Chip::setBandwidth ( Radio::LoRaBW_t bw)

기본으로 사용할 LoRa bandwidth (BW)를 설정합니다.

전송할 프레임의 meta.LoRa.bw 에 유효한 Radio::LoRaBW_t 를 지정하지 않으면 이 함수에서 지정한 BW가 사용됩니다.

Parameters
sfLoRa bandwidth
Returns
  • ERROR_SUCCESS : 설정 성공
  • ERROR_FAIL : 설정 실패 (칩이 이미 시작됨)

◆ setChannel()

void SX1301Chip::setChannel ( uint32_t channel)
virtual

채널을 설정합니다.

Implements PacketRadioChip.

◆ setCodingRate()

error_t SX1301Chip::setCodingRate ( Radio::LoRaCR_t cr)

기본으로 사용할 LoRa coding rate (CR)를 설정합니다.

전송할 프레임의 meta.LoRa.cr 에 유효한 Radio::LoRaCR_t 를 지정하지 않으면 이 함수에서 지정한 CR가 사용됩니다.

Parameters
sfLoRa coding rate
Returns
  • ERROR_SUCCESS : 설정 성공
  • ERROR_FAIL : 설정 실패 (칩이 이미 시작됨)

◆ setDataRate()

error_t SX1301Chip::setDataRate ( Radio::LoRaSF_t sf)

기본으로 사용할 LoRa spreading factor (SF)를 설정합니다.

전송할 프레임의 meta.LoRa.sf 에 유효한 Radio::LoRaSF_t 를 지정하지 않으면 이 함수에서 지정한 SF가 사용됩니다.

Parameters
sfLoRa spreading factor
Returns
  • ERROR_SUCCESS : 설정 성공
  • ERROR_FAIL : 설정 실패 (칩이 이미 시작됨)

◆ setSyncword()

error_t SX1301Chip::setSyncword ( uint8_t value)

Syncword를 설정합니다.

Parameters
valueSyncword (기본: 0x12, LoRaWAN: 0x34)
Returns
  • ERROR_SUCCESS : 설정 성공
  • ERROR_FAIL : 설정 실패 (칩이 이미 시작됨)

◆ setTxPower()

void SX1301Chip::setTxPower ( int8_t dBm)
virtual

송신 출력을 설정합니다.

Parameters
dBm송신 출력 세기 (단위: dBm)

Implements PacketRadioChip.

◆ sleep()

void SX1301Chip::sleep ( )
virtual

Implements PacketRadioChip.

◆ transmit()

error_t SX1301Chip::transmit ( RadioPacket * pkt)
virtual

Implements PacketRadioChip.

◆ wakeup()

void SX1301Chip::wakeup ( )
virtual

Implements PacketRadioChip.

The documentation for this class was generated from the following file:
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