MCP391x Class Reference

SPI driver for MCP391x multi-channel ADCs. Call begin() before reads. I2C operation and the declared streaming entry points are not implemented. More...

#include <MCP391x.hpp>

Public Types
enum	Chip_t {   MCP3918 , MCP3910 , MCP3919 , MCP3912 ,   MCP3913 , MCP3914 }
	ADC model and channel count; only SPI transport is supported. More...
enum	Pre_t { PRE_DIV1 = 0ul , PRE_DIV2 = 1ul , PRE_DIV4 = 2ul , PRE_DIV8 = 3ul }
	ADC master-clock prescaler settings. More...
enum	Osr_t {   OSR_32 = 0ul , OSR_64 = 1ul , OSR_128 = 2ul , OSR_256 = 3ul ,   OSR_512 = 4ul , OSR_1024 = 5ul , OSR_2048 = 6ul , OSR_4096 = 7ul }
	ADC oversampling ratio settings. More...

Public Member Functions
	MCP391x (Chip_t type, SPI &spi, int8_t cs, int8_t dr, bool drHiZ=true, int8_t reset=-1)
	Bind an ADC model, SPI bus, and GPIO wiring.
bool	begin (bool useCrystal=false, Pre_t pre=PRE_DIV1, Osr_t osr=OSR_256)
	Configure GPIO and ADC prescaler/oversampling after checking the security register.
void	streamStart (unsigned reg)
	Streaming entry point declared without an implementation; do not call.
void	streamEnd ()
	Streaming entry point declared without an implementation; do not call.
uint32_t	readChannel (unsigned channel, unsigned len)
	Read raw channel bytes synchronously without sign conversion.

Detailed Description

SPI driver for MCP391x multi-channel ADCs. Call begin() before reads. I2C operation and the declared streaming entry points are not implemented.

Member Enumeration Documentation

Chip_t

enum MCP391x::Chip_t

ADC model and channel count; only SPI transport is supported.

               { MCP3918, // 1 channel (SPI/TWI)
                 MCP3910, // 2 channels (SPI/TWI)
                 MCP3919, // 3 channels (SPI/TWI)
                 MCP3912, // 4 channels (SPI)
                 MCP3913, // 6 channels (SPI)
                 MCP3914, // 8 channels (SPI)
  } Chip_t;

Osr_t

enum MCP391x::Osr_t

ADC oversampling ratio settings.

               { OSR_32 =   0ul,
                 OSR_64 =   1ul,
                 OSR_128 =  2ul,
                 OSR_256 =  3ul,
                 OSR_512 =  4ul,
                 OSR_1024 = 5ul,
                 OSR_2048 = 6ul,
                 OSR_4096 = 7ul } Osr_t;

Pre_t

enum MCP391x::Pre_t

ADC master-clock prescaler settings.

               { PRE_DIV1 = 0ul,
                 PRE_DIV2 = 1ul,
                 PRE_DIV4 = 2ul,
                 PRE_DIV8 = 3ul } Pre_t;

Constructor & Destructor Documentation

MCP391x()

MCP391x::MCP391x ( Chip_t type, SPI & spi, int8_t cs, int8_t dr, bool drHiZ = true, int8_t reset = -1 )

inline

Bind an ADC model, SPI bus, and GPIO wiring.

Parameters

type	ADC model.
spi	Bus that outlives the driver.
cs	Active-low chip-select pin.
dr	Data-ready input pin.
drHiZ	Stored data-ready mode flag; currently not applied to hardware.
reset	Optional reset pin; -1 omits hardware reset.

    : spi(spi), PIN_RESET(reset), PIN_CS(cs), PIN_DR(dr), drHiZ(drHiZ),
      NumChannels((type == MCP3918) ? 1 :
                  (type == MCP3910) ? 2 :
                  (type == MCP3919) ? 3 :
                  (type == MCP3912) ? 4 :
                  (type == MCP3913) ? 6 :
                  (type == MCP3914) ? 8 : 0) {
  }

Member Function Documentation

begin()

bool MCP391x::begin	(	bool	useCrystal = false,
		Pre_t	pre = PRE_DIV1,
		Osr_t	osr = OSR_256 )

Configure GPIO and ADC prescaler/oversampling after checking the security register.

Parameters

useCrystal	True selects the internal crystal oscillator; false leaves the clock setting unchanged.
pre	Master-clock prescaler.
osr	Oversampling ratio.

Returns

True if the security register is 0xA50000 and configuration was attempted.

readChannel()

uint32_t MCP391x::readChannel	(	unsigned	channel,
		unsigned	len )

Read raw channel bytes synchronously without sign conversion.

Parameters

channel	Zero-based channel index valid for the selected model.
len	Transfer width in bytes: 2, 3, or 4, matching device configuration.

Returns

Raw bits assembled into a uint32_t; arguments are not validated.

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The documentation for this class was generated from the following file:

• include/dev/MCP391x.hpp